Table of Contents

• 6502 Instruction Set Mnemonics
  • Sorted Alphabetically
  • Sorted By Kind of Instruction
• 6502 Opcodes and Addressing Modes
• 6502 Assembly Primer
  • Some References
• 6502 Instruction Mnemonics and Definitions

GEOS runs on the Commodore 64, Commodore 128, Commodore Plus/4, and Apple IIe computers, as well as the computers completely compatible with them. They all use a CPU from the 6502 family of microprocessors: the 6502 (Apple IIe), the 65C02 (Apple IIe Enhanced and Apple IIc), the 6510 (Commodore 64), the 7501 or 8501 (Commodore Plus/4), the 8502 (Commodore 128), the 65CE02 AKA 4510 (Commodore 65), and the 65C816 (CMD SuperCPU and Apple IIgs).

The most common language to program in for GEOS is in 6502 assembly language with a macro assembler.

This page is intended to be a quick reference, not a tutorial or necessarily complete reference.

Most of the data on this page is from the Commodore 64 Programmer's Reference Guide and is specific to the 6510 CPU. The only programmer-visible difference between the 6502 and 6510 is the placement of hardware I/O at memory addresses $0000 and $0001, making them unavailable for use as storage.

Important: The earliest CPUs in the 6502 series don't have a bra instruction, including those used in the Commodore 64 and 128, but the later CPUs do. However, this guide's example code appears to make use of a bra instruction in CPUs that don't have one. Where it's used in this guide, it refers to to a geoProgrammer macro called "bra" instead. The macro expands to a clv followed by bvc instruction. (Same for "smb," "rmb," "bbs," and "bbr," although no 6502-series CPUs found in Commodore or Apple 8-bit computers actually use those mnemonics.)

6502 Instruction Set Mnemonics

Sorted Alphabetically

• adc
• and
• asl
• bcc
• bcs
• beq
• bit
• bmi
• bne
• bpl
• brk
• bvc
• bvs
• clc
• cld
• cli
• clv
• cmp
• cpx
• cpy
• dec
• dex
• dey
• eor
• inc
• inx
• iny
• jmp
• jsr
• lda
• ldx
• ldy
• lsr
• nop
• ora
• pha
• php
• pla
• plp
• rol
• ror
• rti
• rts
• sbc
• sec
• sed
• sei
• sta
• stx
• sty
• tax
• tay
• tsx
• txa
• txs
• tya

Sorted By Kind of Instruction

6502 Opcodes and Addressing Modes

Empty opcodes in the tables above map to undefined instructions that are often called "illegal opcodes." The 6502 doesn't use CPU microcode in the modern sense, so it will try to perform illegal opcode instructions if it encounters one. The instructions carried out by illegal opcodes are undefined, often vary between CPU models in the 6502 family, and in some cases cause unpredictable behavior. For example, one such set of opcodes, nicknamed with the mnemonic "jam," jams the CPU into a non-functional state; a reset or power cycle is the only way to recover.

Some of the empty opcodes in the tables above are defined and used by later CPUs in the 6502 family for added functionality, such as access to more registers, wider registers, and larger addressable memory ranges. At the time this guide was written, the 65C816 was a currently produced and commercially available CPU compatible with the 6502.

Except for Implied and Accumulator modes, which don't take an operand, and Immediate mode, which takes a value as an operand, all addressing modes take a memory address as an operand.

In Indirect, Indexed Indirect, and Indirect Indexed modes, the values at the operand address and the operand address plus one are taken as a word pointer to an absolute address in memory. The order of bytes is low byte at low address and high byte at high address, or offset byte followed by page byte. In Indirect mode (used only by the JMP instruction), the pointer is used as the jump vector. In Indexed Indirect mode, the value of X is added to the operand to find the addresses containing the pointer. In Indirect Indexed mode, the operand is the address of the pointer's low byte, and the value of Y is instead added to the pointer value, not the operand.

The address in Relative mode is a signed byte computed as an offset from the instruction following a branch instruction. A relative address can be between 126 bytes behind the branch instruction opcode (-128+2) to 129 bytes ahead of it (127+2). Virtually every assembler will let you assign a label to the branch target address and use that label as the branch instruction operand, saving you the trouble of converting an absolute address into a relative address. In the assembler mode of most machine language monitors, the monitor will let you enter a branch to an absolute address and convert the operand to a relative address for you as well.

In Zero Page Indexed and Indexed Indirect modes, adding the index value to the operand address could result in a computed address of 256 ($100) or greater. If that happens, the actual computed address will remain in page 0 and simply wrap around from $00ff to $0000. For example, if you run lda $70,x when X contains $f1, then the value A is loaded with will not come from address $0161 as you might think; the overflowing $1 would be discarded, and A would be loaded from address $0061 instead.

Note that this wrap-around will not happen in Indirect Indexed mode. In Indirect Indexed mode, the values at the operand address and operand address plus one are taken as a pointer to an absolute address, then the value of Y is added to that absolute address. For example, if $02 contains $81 and $03 contains $a0, together forming a pointer to $a081, and Y contains $c1, then running sta ($02),y would store the value of A in address $a142: Y ($c1) plus the adddress word at $02 ($a081).

6502 Assembly Primer

The 6502 is an 8-bit CPU comprised of six registers, a set of 151 CPU operation codes (called "opcodes") expressed as 56 instructions, and one to eight of 13 addressing modes for each instruction. Three of the registers are directly accessible by the programmer, and three are not. Five of the registers are 8-bit byte-size registers, and one is 16-bit word-size.

The Accumulator, the X Index, and the Y Index are the registers directly accessible by the programmer: They can be directly loaded with byte values, and their values can be directly stored in memory.

The Accumulator, also called the A register, is the only register that can be directly involved in basic arithmetic operations, and it's the register most often used for general data transformations. The X and Y registers are used most often for holding counters or offsets for accessing memory, but they can also be used for shuttling data like the A register. The X register is also the only register that can retrieve or change the Stack Pointer.

The Processor Status register contains seven bit flags indicating various current or recent CPU events. Most instructions either cause a status flag to change or examine a status flag to determine a course of action.

The Negative flag is set or cleared based on bit 7 of A.

The Overflow flag is set when the two's-complement result of an addition or subtraction is invalid; that is, when adding two like-signed numbers or subtracting two different-signed numbers gives an answer greater than 127 or less than -128.

BCD stands for "binary-coded decimal" and is an encoding in which each nybble is limited to holding a decimal digit ($0--$9). In binary math, adding $05 to $07 gives $0c (12). In BCD math, however, the hex values $a--$f are invalid, so adding $05 to $07 gives the hex value $12 (18, the BCD encoding for 12). The ADC and SBC instructions are the only ones that use Decimal Mode. In GEOS, the D flag is clear by default. If your program enables it with SED, it must disable it again with CLD before calling any GEOS Kernal routines, or the routines may perform bad math.

The 6502 has two types of interrupts: maskable interrupt requests, called IRQ, and non-maskable interrupt requests, called NMI. The Interrupt Disable flag affects only IRQs. NMIs will always interrupt the CPU, and the BRK instruction causes an NMI. Note that because the Interrupt Disable flag is for disabling IRQ, the SEI and CLI instructions do the opposite of what you might expect: SEI disables IRQ, and CLI enables IRQ.

The stack is a first-in last-out structure. The byte most recently pushed to the stack is the first that will be popped ("pulled" in 6502) from the stack and is said to be at the top of the stack. The Stack Pointer starts at the end of the stack page ($01), pointing to $01ff. Every time a byte is pushed onto the stack, 1 is subtracted from the Stack Pointer, so it points to the first free byte in the stack page. Every time a byte is pulled from the stack, the reverse happens: 1 is added to the Stack Pointer. Be careful with stack management: If more than 256 bytes are pushed onto the stack, then the Stack Pointer will overflow and wrap around from $0100 to $01ff, and the bottom of the stack will be overwritten and lost.

The limited set of registers and instructions means that a 6502 programmer has to use an assortment of clever tricks and boilerplate code to accomplish tasks that more complicated CPUs can perform natively, but it still contains all the resources necessary to accomplish them.

To help deal with the limited number and capabilities of the registers, the 6502 lets you use the first page of memory (page 0 or Zero Page) as pseudo-registers via Zero Page addressing modes, which are shorter and faster than their corresponding Absolute addressing modes.

Programs are most often written for a programming language compiler or assembly langugage assembler and linker. Most assemblers take code in the form of three-letter instruction mnemonics, followed by an operand and punctuation indicating the instruction addressing mode. Instructions taking operands must have either a byte-size or word-size number for the operand; most assemblers allow you to define names to stand in for those numbers, which you can then use as constants, variables, routines, global labels, local labels, and other kinds of named values.

Source code lines are divided into four fields: an address label, an instruction, its operand, and a comment. Lines can have any, all, or none of those fields, each separated by any amount of spacing, but they appear in that order. (However, operands can't appear alone; an operand must be on the same line as its instruction.) Most assemblers will not let you write more than one instruction per line of source code.

Every addressing mode taking a numeric operand except one will use that numeric value as an address. Immediate mode is the exception: It uses the numeric value literally, loading the affected register with that value. In most assemblers and machine language monitors, you need to use a hash sign or octothorpe (" # ") to signal Immediate mode addressing. A leading "#" indicates an immediate decimal value, a leading "#$" digraph means an immediate hexadecimal value, a leading "#%" digraph means an immediate binary value, and (in geoAssembler) a leading "#?" digraph means an immediate octal value. For example, lda #15, lda #$0f, lda #%00001111, and lda #?017 compile to the exact same instruction opcode and operand bytes ($a9 $0f).

The comment character for 6502 code is universally the semi-colon. A comment begins with a semi-colon (" ; "), and it ends with the line terminator (ASCII code CR in GEOS). Assembler-specific directives can be abused to produce multi-line comments, but only the semi-colon single-line comments are ubiquitous.

See other references for more complete primers and actual tutorials for 6502 assembly language programming. Unless you engage in the surprisingly practical madness of compiling your own assembly code by hand, you should get an assembler and read its manual as well.

Some References

• 6502.org: The 6502 Microprocessor Resource
• Assembly In One Step [Plain Text]
• Easy6502 [JavaScript required for in-browser emulator]
• geoProgrammer Users Manual [JavaScript required for in-browser reading]
• geoProgrammer Users Manual (download) [PDF]

6502 Instruction Mnemonics and Definitions

Each mnemonic is described with a summary and two tables. The data is from the Commodore 64 Programmer's Reference Guide and applies to the 6510 CPU.

First table:

• Operation: A brief expression of the instruction's operation.
  • A, X, Y, P, S, PC: Given regester or its value.
  • N, V, B, D, I, Z, C: Given bit flag of P register or its value.
  • M: Given memory address or its value, or value of Immediate mode operand.
• Flags: A list of flags affected and how.

Second table:

• Mode: An addressing mode available for this instruction.
• Assembly Form: How the instruction is written in source code for this mode.
  • Oper: A stand-in symbol or label for the operand value byte.
  • OperW: A stand-in symbol or label for the operand value word.
• Hex: The opcode in hexadecimal form.
• Bytes: The total number of bytes used for the opcode and operand.
• Cycles: The total number of CPU cycles it takes to perform the instruction.

Flags:

• N: Negative
• V: Overflow
• B: Break
• D: Decimal
• I: Interrupt
• Z: Zero
• C: Carry

adc

Add memory to accumulator with carry. This is the only addition instruction; there is no addition without carry. Performs binary addition when D = 0; performs binary-coded decimal (BCD) addition when D = 1. The complementary math instruction is sbc.

and

Logical AND to the accumulator.

asl

Arithmetic shift left, or shift memory or accumulator left one bit. This differs from rol in that a 0 is shifted in. The effect is multiplication by 2, or by a power of 2 when repeated. The complementary shift instruction is lsr.

bcc

Branch on carry clear.

bcs

Branch on carry set.

beq

Branch on equal or result zero.

bit

Test bits in memory with accumulator.

bmi

Branch on minus or result negative.

bne

Branch on not equal or result not zero.

bpl

Branch on plus or result positive.

brk

Force break interrupt. A brk command can't be masked by setting I.

bvc

Branch on overflow clear.

bvs

Branch on overflow set.

clc

Clear carry flag.

cld

Clear decimal mode. After this instruction, adc and sbc perform binary arithmetic.

cli

Clear interrupt disable bit. This instruction enables IRQ; use sei to disable IRQ.

clv

Clear overflow flag.

cmp

Compare memory and accumulator.

cpx

Compare memory and X Index.

cpy

Compare memory and Y Index.

dec

Decrement memory by one.

dex

Decrement X Index by one.

dey

Decrement Y Index by one.

eor

Logical exclusive-OR to the accumulator.

inc

Increment memory by one.

inx

Increment X Index by one.

iny

Increment Y Index by one.

jmp

Jump to new location.

jsr

Jump to new location saving return address, or jump to subroutine.

lda

Load accumulator with memory.

ldx

Load X Index with memory.

ldy

Load Y Index with memory.

lsr

Logical shift right, or shift memory or accumulator right one bit. This differs from ror in that a 0 is shifted in. The effect is division by 2, or by a power of 2 when repeated. The complementary shift instruction is asl.

nop

No operation. Take two cycles and do nothing.

ora

Logical OR to the accumulator.

pha

Push accumulator to stack.

php

Push processor flags to stack.

pla

Pull accumulator from stack. Other CPU architectures call this "pop."

plp

Pull processor flags from stack. Other CPU architectures call this "pop."

rol

Rotate memory or accumulator left one bit. This differs from asl in that C is shifted in.

ror

Rotate memory or accumulator right one bit. This differs from lsr in that C is shifted in. This instruction is not available on 6502-series CPUs made before July 1976.

rti

Return from interrupt.

rts

Return to saved, or return from subroutine.

sbc

Subtract memory from accumulator with carry. This is the only subtraction instruction; there is no subtraction without carry. Performs binary subtraction when D = 0; performs binary-coded decimal (BCD) subtraction when D = 1. The carry is used as a borrow, and its meaning is inverted: 1 is borrowed when C = 0, and 0 is borrowed when C = 1. The complementary math instruction is adc.

sec

Set carry flag.

sed

Set decimal mode. After this instruction, adc and sbc perform binary-coded decimal (BCD) arithmetic.

sei

Set interrupt disable bit. This instruction disables IRQ; use cli to enable IRQ.

sta

Store accumulator in memory.

stx

Store X Index in memory.

sty

Store Y Index in memory.

tax

Transfer accumulator to X Index.

tay

Transfer accumulator to Y Index.

tsx

Transfer stack pointer to X Index.

txa

Transfer X Index to accumulator.

txs

Transfer X Index to stack pointer.

tya

Transfer Y Index to accumulator.